A synchronous random access memory (SRAM) can transmit/receive read/write data once per clock period. A double data rate SRAM may be able to transmit data at twice the rate of an SRAM by transmitting data on the rising and falling edges of the clock (rather than on only one edge). However, in some memory devices, data is input/output via a common (e.g., a single) pin. When a common input/output port (common I/O) is used, the input and output operations of the data may not be easily controlled independently of one another, thus limiting the rate at which data can be input/output to/from the device.
Accordingly, it is known to use separate I/O for devices such as an SRAM so that an input pin and an output pin are separated from each other so that the input/output of the data can be controlled independently. Memory devices having the separated input/output pins may be capable of receiving a read command/address and a write command/address (with write data) in one period of the clock, thus increasing the device's operating speed.
However, even if the memory device has the separate I/O, when the memory device receives the read command/address and the write command/address/data, access to the memory cell region may be performed twice in order to perform the read operation and the write operation in one clock period, which may require the word line to be cycled twice during the clock period.
FIG. 1 is a timing view of operations of a conventional memory device having separate I/O. A relation between the address and the word line or a latency of the input data or the output data can be changed by construction of the memory device, (which is not shown or reflected in FIG. 1).
Referring to FIG. 1, a write address (WADD) and a read address (RADD) are input during one period of a clock signal (CLK). Addresses RADDs A0, A2, A4, and A6 are input on a rising edge of the CLK. Addresses WADDs A1, A3, A5, and A7 input on a falling edge of the CLK. RES and WES represent a read selection signal and a write selection signal for selecting RADD and WADD, respectively.
The word line AWL0 is activated by RADD A0, and the data Q0 is output corresponding to the word line AWL0. Also, when the word line AWL1 is activated corresponding to WADD A1, the input data D1 is input. The word line AWL0 (for a read operation) and the word line AWL1 (for a write operation) are both activated during the one period of the CLK. Therefore, the period of CLK may not be less than a total activation time of the two word lines, which may limit the operating speed of the integrated circuit.
Accordingly, data transmission speeds may be increased by separating the data transmission path, in the same manner that separate I/O is used to increase the operating speed of the integrated circuit, and may be further increased by using both the rising and the falling edges of the clock signal to control data transmission. However, according to the above method, the read and write operations may not be performed simultaneously in the memory cell region, which may limit the operating speed.
It is known to use a temporary memory for the read and the write operations so that the memory cell region may be accessed simultaneously, thus increasing the operational speed of the integrated circuit. In some conventional integrated circuits, a temporary memory having a faster operational speed than that of a main memory is added, a predetermined part of the main memory is mapped to the temporary memory, and the read and write operations can be performed using the temporary memory.
For example, for read operations, if the desired data is stored in the temporary memory, the data is read from the temporary memory, and if the desired data is not in the temporary memory, the data is read from the main memory and new data is updated in the temporary memory. For write operations, data from an external source is written to the temporary memory. When there is no space to write data in the temporary memory, data which is not used frequently can be transferred to the main memory.
The above method is characteristic in cases where addressing proceeds linearly such that a next address is incremental over a recently used address. However, in a case where the address generation is random, the operational speed may be lowered greatly. Alternatively, the operational speed may also be reduced if the memory access involves multiple memory regions across a plurality of bytes. Also, if write/read operations are to be performed simultaneously to the main memory, a temporary memory may be needed if, for example, the write/read addresses are within the same row.
In addition, the data stored in the temporary memory can be transferred to the main memory unless the subsequent write and read operations are directed to regions of memory where simultaneous access is not allowed. Here, the temporary memory is the same size as the minimum size of a space where the write and read operations may not be performed simultaneously in the main memory. Also, a tag memory that stores an address in the main memory (in which the data stored in the temporary memory will be stored), is disposed to increase the operational speed of the integrated circuit.
FIG. 2 is a circuit diagram for describing some problems associated with simultaneous write and read operations. FIG. 2 shows a structure of a static random access memory (SRAM). The main memory of the SRAM has a matrix structure for storing the data effectively, and has a minimum area on which the write and read operations cannot be performed simultaneously. The minimum area is shown in FIG. 2.
A first latch L1, in which data is stored, is connected between a pair of bit lines BL and/BL using transistors TR1 and BTR1. It is assumed that data “1” is stored on a left side of the first latch L1 and data “0” is stored on a right side of the first latch L1. It is also assumed that data “0” is stored on a left side of an nth latch Ln and data “1” is stored on a right side of the nth latch Ln. When the first word line WL1 and an nth word line WLn are activated simultaneously, a crash may occur between the data output through the pair of bit lines BL and/BL (because the data values are different). Therefore, two latches may not be accessed in this minimum area of the main memory shown in FIG. 2 simultaneously.
FIG. 3 is a view for describing problems of a second method using the temporary memory. As described in the main memory structure of FIG. 2, a temporary memory (or data memory block) DMB is used to address the problem where the write and read operations cannot be performed simultaneously in the minimum areas SMB1, SMB2, . . . , SMBn of the main memory MB.
That is, when the write address and the read address are received so that the write and read operations are to be performed simultaneously in a sub-memory block SMB1, the read operation is performed in the first sub-memory block SMB1 to read first read data R_DATA1 and the write operation is performed in the temporary memory (DMB) to write first write data W_DATA1 (1).
If a subsequent write and read is directed to a different sub-memory block (for example, nth sub-memory block SMBn) at an address in the same row as that of the first sub-memory block SMB1 on which the read operation is previously performed, the read operation of second read data R_DATA1 can be performed in the nth sub-memory block SMBn. However, the second write operation W_DATA2 cannot be performed in the data memory block (DMB) (2), since the first write data W_DATA1 is stored in the DMB and the second write data W_DATA2 cannot be stored in the DMB.
If a tag memory is used in conjunction with the structure discussed above, the tag memory is searched for the received address, to determine whether the new data is in the DMB or in the sub-memory blocks SMB1, SMB2, . . . , SMBn, the operational speed of the integrated circuit can be further increased. Although the tag memory used with the DMB may increase the operational speed, there may still exist a need for further increases in operating speed.